In a data transmission method that converts information such as an audio signal to digital data and carries out the transmission, an amount of information of the signal to be transmitted is not always fixed in terms of time, but generally varies every moment.
Thus, by dividing the transmission data into individual frames of a fixed time length and carrying out data transmission with a variable number of bits for each frame, it is possible to vary the transmission rate in terms of time, and to transmit the required information during each frame period efficiently. In this case, the transmitting apparatus need not perform useless transmission, and hence can hold down the power consumption of the apparatus.
To achieve the data transmission with varying data transmission rate, it is generally necessary for a receiving side to get information about the transmission rate of each frame by some means. In this case, the following methods have been devised conventionally: a method of transmitting rate information directly transmitted as part of the frame data and making at the receiving side a rate decision from the rate information; and a method (blind rate detecting method) of making at the receiving side a rate decision, without transmitting the rate information, using error detecting code (such as CRC (Cyclic Redundancy Check) code) which is added to the transmission data for indicating communication quality (for example, see Patent Document 1 relating to an application of the present assignee).
On the other hand, in a communication environment causing a lot of transmission errors such as data transmission via a radio transmission channel, an improvement of the transmission quality is generally performed by error correction (FEC: Forward Error Correction) of the transmission data. As the error correcting code and error correcting decoding, a maximum likelihood decoding method such as convolution code and Viterbi decoding is used.
Here, in the method of making the rate decision at the receiving side using the error detecting code added to the transmission data for indicating communication quality without transmitting the rate information, the decision error rate in the rate decision depends on a word length of the error detecting code. In addition, even if the transmission error decreases, it cannot be reduced below a certain predetermined erroneous rate decision rate (probability of making a decision that no transmission error occurred when the rate is wrong).
On the other hand, the method that transmits the rate information from a transmitting side to the receiving side cannot make a decision as to the effective length of the data in a receiving frame if an error occurs during transmission. Thus, even if the data portion includes no error, it becomes difficult for the receiving side to reproduce the transmission data correctly.
In view of this, a method has been devised conventionally that improves the erroneous rate decision rate using likelihood information at the maximum likelihood decoding, and thus varies the transmission rate of each frame during communication more positively (for example, see Patent Document 2 relating to an application of the present applicant).
To improve the rate detecting performance (to reduce the erroneous detection probability of the rate) at the receiving side, the foregoing Patent Documents 1 and 2 describe a method of transmitting the CRC code with placing it at a fixed position in each frame (at the first position of the frame, for example), while CRC code has been conventionally added to the end of the transmission data at the transmitting side (in this case, the position of the CRC code in the frame varies in accordance with the bit length of the transmission data).
FIG. 1A and FIG. 1B are diagrams illustrating conventional transmission bit sequences. In one of the conventional methods (“postposition 1”) that places the CRC code at the end of transmission data bits, the transmitting side transmits the transmission data in sequence of D9 (the most significant bit), . . . , D0 (the least significant bit), followed by the CRC code in sequence of C4 (the most significant bit), . . . , C0 (the least significant bit). The receiving side receives the bit string in this sequence. Then, it assumes the final bit position, and identifies (assumes) the portion corresponding to the CRC code and the portion corresponding to the transmission data according to the assumed final bit position.
According to the assumed transmission data and CRC code, the error detection is carried out. Among the assumed final bit positions, the final bit position is determined to be the position, at which the result of the error detection based on the assumed transmission data and CRC code indicates that no error has occurred.
More specifically, it calculates the CRC code again from the assumed transmission data, and if the CRC code agrees with the assumed CRC code, it determines that the assumed final bit position is the correct final bit position.
Alternatively, instead of calculating the CRC code again, it divides the bit string consisting of the assumed transmission data and assumed CRC code by the generator polynomial, which has been used for calculating the CRC code at the transmitting side. If the bit string is divisible, it makes a decision that no error has occurred, and hence that the assumed final bit position is the correct final bit position. If the bit string is indivisible, it makes a decision that some error has occurred, and hence that the assumed final bit position is not the correct final bit position.
Here, if it detects the position, for example, one bit less than the correct rate position, that is, if it assumes the position one bit shorter than the correct final bit position as the final bit position, a code word row is consecutive such as D1, D0, C4-C1 at the receiving side. Thus, even when no transmission bit error has occurred, the CRC decision result is OK at a probability of 50% (that is, erroneous detection). Likewise, at the position 2 bits less, the CRC decision result is OK at the probability of 25%, and at the position 3 bits less, it is OK at the probability of 12.5%.
FIG. 2 is a diagram illustrating an example of the transmitted signal and received signal according to the conventional transmission bit sequence (postposition 1). In the example of FIG. 2, the transmitting side transmits “1 (the most significant bit), 0, 0, 0, 1, 0, 0, 1, 0, 0 (the least significant bit)” corresponding to the transmission data in this order, followed by transmitting “1 (the most significant bit), 0, 1, 1, 0 (the least significant bit)” corresponding to the CRC code in this order. The receiving side receives the bit string in this order.
The example of FIG. 2 encodes the 10-bit transmission data G(X) using a generator polynomial P(X). The generator polynomial P(X), transmission data G(X), CRC code R(X) calculated from them, and finally transmitted signal F1(X) are expressed as follows.
                              P          ⁡                      (            X            )                          =                ⁢                              X            5                    +                      X            4                    +                      X            2                    +          1                                                  G          ⁡                      (            X            )                          =                ⁢                              X            9                    +                      X            5                    +                      X            2                                                            R          ⁡                      (            X            )                          =                ⁢                              X            4                    +                      X            2                    +          X                                                  F          ⁢                                          ⁢          1          ⁢                      (            X            )                          =                ⁢                                            X              5                        ⁢                          G              ⁡                              (                X                )                                              +                      R            ⁡                          (              X              )                                                              =                ⁢                              (                                          X                14                            +                              X                10                            +                              X                7                                      )                    +                      (                                          X                4                            +                              X                2                            +              X                        )                              
When the correct final bit position is assumed at the receiving side that receives such a transmitted signal, the received signal H1(X) can be expressed as follows.H1(X)=X14+X10+X7+X4+X2+X 
The received signal H1(X) is divisible by the generator polynomial P(X) as follows.
                              H          ⁢                                          ⁢          1          ⁢                      (            X            )                          =                ⁢                              X            14                    +                      X            10                    +                      X            7                    +                      X            4                    +                      X            2                    +          X                                        =                ⁢                              (                                          X                5                            +                              X                4                            +                              X                2                            +              1                        )                    ⁢                      (                                          X                9                            +                              X                8                            +                              X                7                            +                              X                3                            +                              X                2                            +              X                        )                                                  =                ⁢                              P            ⁡                          (              X              )                                ⁢                      (                                          X                9                            +                              X                8                            +                              X                7                            +                              X                3                            +                              X                2                            +              X                        )                              
Thus, the receiving side makes a decision of no error, and hence determines the assumed position as the correct final bit position. The decision of the final bit position is correct.
On the other hand, when assuming the position one bit less than the correct final bit position as the final bit position, the received signal H1′(X) can be expressed as follows.H1′(X)=X13+X9+X6+X3+X+1
The received signal H1′(X) is divisible by the generator polynomial P(X) as follows.
                              H          ⁢                                          ⁢                      1            ′                    ⁢                      (            X            )                          =                ⁢                              X            13                    +                      X            9                    +                      X            6                    +                      X            3                    +          X          +          1                                        =                ⁢                              (                                          X                5                            +                              X                4                            +                              X                2                            +              1                        )                    ⁢                      (                                          X                8                            +                              X                7                            +                              X                6                            +                              X                2                            +              X              +              1                        )                                                  =                ⁢                              P            ⁡                          (              X              )                                ⁢                      (                                          X                8                            +                              X                7                            +                              X                6                            +                              X                2                            +              X              +              1                        )                              
Thus, the receiving side makes a decision of no error, and hence determines the assumed position as the correct final bit position.
The decision of the final bit position is an error. That is, it is an erroneous detection.
To solve such a problem in that the probability of the erroneous detection increases as the assumed position approaches the correct rate position, the foregoing Patent Document 1 and 2 conceive a method of placing the CRC code at the initial position of the frame (“preposition”). In this method, as shown in (preposition of) FIG. 1B, the code word row is inconsecutive like D1, C4-C1 at the receiving side. Accordingly, the foregoing problem does not occur, and a low erroneous detection probability, which is determined by the word length of the CRC code, can be obtained constantly from the detecting position close to the correct rate position through a distant detecting position.
However, to always transmit the CRC code with placing it at the initial position of the frame at the transmitting side in practice, that is, to transmit the CRC code placing it before the transmission data, it is necessary to store all the bits of the transmission data temporarily in a memory until the calculation of the error detecting code for the transmission data is completed. Such a buffer memory demands a large capacity in proportion to the number of bits of the transmission data in one frame. Thus, to transmit an enormous amount of transmission data, the scale of the hardware becomes a problem.
To solve such problem, Patent Documents 3 and 4 relating to applications of the present applicant describe a method of placing the error detecting code (such as CRC code) after the transmission data, and conducting the transmission placing the bit series of the transmission data and that of the error detecting code in inverse order.
In Patent Documents 3 and 4, the error detecting code is placed after the transmission data, and the R-bit series of the error detecting code before the final bit position is rearranged in inverse order, where R is equal to the number of bits C of the error detecting code.
FIG. 3A and FIG. 3B are examples illustrating the conventional transmission bit sequences. According to the placements of the inventions described in Patent Documents 3 and 4 (“postposition 2”), the sequence of the CRC code is rearranged in inverse order at the transmitting side. Thus, the transmission data is transmitted in the order of D9 (the most significant bit), . . . , D0 (the least significant bit), followed by transmitting the CRC code in the order of C0 (the least significant bit), . . . , C4 (the most significant bit).
The receiving side receives the bit string in this order. Then, it assumes the final bit position, and according to the assumed final bit position, it identifies (assumes) the portion corresponding to the CRC code and the portion corresponding to the transmission data, and rearranges the portion corresponding to the CRC code in inverse order. After that, the processing is the same as that of the foregoing “postposition 1”.
According to the method of Patent Documents 3 and 4, the receiving side decides the CRC code as C3-C0, D0 which is obtained by rearranging D0, C0-C3 in inverse order. As a result, the code word sequence at the receiving side becomes inconsecutive, such as . . . , D1, C3, . . . , C0, D0. Thus, it is possible to prevent the problem in which the erroneous detection probability increases as the detecting position approaches the correct rate position, and to obtain a low erroneous detection probability, which is determined by the word length of the CRC code, constantly from the detecting position close to the correct rate position through the distant detecting position as in the case where the CRC code is placed before the transmission data.
In addition, since the arrangement according to the inventions described in Patent Documents 3 and 4 places the CRC after the transmission data, it can eliminate the need for providing the buffer for temporarily storing the transmission data while maintaining the high rate detecting performance as mentioned above, thereby allowing implementation in a hardware component with a small circuit scale.
FIG. 4 is a diagram illustrating an example of the transmitted signal and received signal according to conventional transmission bit sequence (postposition 2). In the example of FIG. 4, the transmitting side transmits “1 (the most significant bit), 0, 0, 0, 1, 0, 0, 1, 0, 0 (the least significant bit)” corresponding to the transmission data in this order, followed by “0 (the least significant bit), 1, 1, 0, 1 (the most significant bit)” corresponding to the CRC code rearranged in inverse order in this order. The receiving side receives the bit string in this order.
The example of FIG. 4 encodes 10-bit transmission data G(X) using a generator polynomial P(X) in the same manner as that of FIG. 2. As for the CRC code R(X) calculated, the processing is the same as that of FIG. 2. As for the transmitted signal F2(X), however, the CRC code is rearranged in inverse order as follows.F2(X)=(X14+X10+X7)+(X3+X2+1)
When the receiving side, which receives such a transmitted signal, assumes the correct final bit position, the received signal H2(X) can be expressed as follows.H2(X)=X14+X10+X7+X3+X2+1
As for the received signal H2(X), rearranging the CRC code portion in inverse order gives the following expression.K2(X)=X14+X10+X7+X4+X2+X 
The expression K2(X) is equivalent to the foregoing H1(X), and is divisible by the generator polynomial P(X) as follows.
                              K          ⁢                                          ⁢          2          ⁢                      (            X            )                          =                ⁢                              X            14                    +                      X            10                    +                      X            7                    +                      X            4                    +                      X            2                    +          X                                        =                ⁢                              (                                          X                5                            +                              X                4                            +                              X                2                            +              1                        )                    ⁢                      (                                          X                9                            +                              X                8                            +                              X                7                            +                              X                3                            +                              X                2                            +              X                        )                                                  =                ⁢                  P          ⁢                      (            X            )                    ⁢                      (                                          X                9                            +                              X                8                            +                              X                7                            +                              X                3                            +                              X                2                            +              X                        )                              
Thus, the receiving side makes a decision that no error has occurred, and that the assumed position is the correct final bit position. The decision as to the final bit position is correct.
On the other hand, if the position one bit shorter than the correct final bit position is assumed as the final bit position, the received signal H2′(X) can be expressed as follows.H2′(X)=X13+X9+X6+X2+X 
As for the received signal H2′(X), rearranging the CRC code portion in inverse order gives the following expression.K2′(X)=X13+X9+X6+X3+X2 
The expression K2′(X) is indivisible by the generator polynomial P(X) as follows.
                              K          ⁢                                          ⁢                      2            ′                    ⁢                      (            X            )                          =                ⁢                              X            13                    +                      X            9                    +                      X            6                    +                      X            3                    +                      X            2                                                  =                ⁢                                            (                                                X                  5                                +                                  X                  4                                +                                  X                  2                                +                1                            )                        ⁢                          (                                                X                  8                                +                                  X                  7                                +                                  X                  6                                +                                  X                  2                                +                X                +                1                            )                                +                                                ⁢                  (                                    X              2                        +            X            +            1                    )                                        =                ⁢                                            P              ⁡                              (                X                )                                      ⁢                          (                                                X                  8                                +                                  X                  7                                +                                  X                  6                                +                                  X                  2                                +                X                +                1                            )                                +                      (                                          X                2                            +              X              +              1                        )                              
Thus, the receiving side makes a decision that an error has occurred, and hence does not make a decision that the assumed position is the correct final bit position.
In this way, an erroneous detection of the final bit position can be prevented.
Patent Document 1: International Patent Laid-Open No. 96/26582 pamphlet.
Patent Document 2: International Patent Laid-Open No. 97/50219 pamphlet.
Patent Document 3: International Patent Laid-Open No. 00/79720 pamphlet.
Patent Document 4: Japanese Patent Laid-Open No. 2002-158642.